Cdm Bread Crumb Register—Mbar + 0X0208; Cdm Configuration Register—Mbar + 0X020C - Freescale Semiconductor MPC5200B User Manual

CDM Registers
Bit Name
27 ppc_pll_cfg_0
28 ppc_pll_cfg_1
29 ppc_pll_cfg_2
30 ppc_pll_cfg_3
31 ppc_pll_cfg_4
5.5.3 CDM Bread Crumb Register—MBAR + 0x0208
The CDM Bread Crumb Register is a 32-bit register that is not reset. Its purpose is to let firmware designers leave some status code before
entering a reset condition. Since this register is never reset, the value written is available after the reset condition has ended. There is no
additional functionality to this register.
msb 0 1
R
W
RESET: — —
16 17
R
W
RESET: — —
5.5.4 CDM Configuration Register—MBAR + 0x020C
The CDM Configuration Register contains 3 bits that set IPB_CLK and PCI_CLK ratios.
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
5-14
e300 Core core pll config pins. See also
Table 5-10. CDM Bread Crumb Register
2 3 4 5 6
CDM Bread Crumb Register (Never Reset)
— — — — —
18 19 20 21 22
CDM Bread Crumb Register (Never Reset)
— — — — —
Table 5-11. CDM Configuration Register
2 3 4 5
Reserved
Write 0
0 0 0 0
18 19 20 21 22
Reserved
Write 0
0 0 0 0
MPC5200B Users Guide, Rev. 1
Description
Table 5-6
7 8 9 10
— — — —
23 24 25 26
— — — —
6 7 8 9 10
0 0 0 0 0
23 24 25 26
Reserved
0 1 0 0 0
11 12 13 14
— — — —
27 28 29 30
— — — —
11 12 13 14
Reserved
Write 0
0 0 0 0
27 28 29 30
Write 0 clk_sel
0 0 0 0
Freescale Semiconductor
15
—
31 lsb
—
15
V
31 lsb
pci_
1