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ATA RESET/Power-Up
Ultra DMA mode 2 (UDMA2) requires that the ip bus clock speed is at least 66MHz.
Table 11-39
lists the redefined ultra DMA protocol signal lines. These lines provide new functions during the ultra DMA mode. At termination
of an ultra DMA burst, the host negates DMACK and the lines revert to the definitions used for non-ultra DMA transfers.
Table 11-39. Redefinition of Signal Lines for Ultra DMA Protocol
Non-Ultra DMA modes
DIOR
IORDY
DIOW
Both the host and drive do a CRC function during an ultra DMA burst:
•
The host sends CRC data to the drive.
•
The drive does a CRC data comparison.
If the CRC comparison fails, the error register ERR bit is set. The drive always reports the first error that occurs.
11.8
ATA RESET/Power-Up
11.8.1
Hardware Reset
RESET
The host asserts
for a minimum of 25µs after power has stabilized within system specified tolerance. A signal assertion less than
20ns is not recognized by the drive.
The host should not do the following:
•
set the device control register bit SRST to 1 to enable the drive for software reset
•
issue a DEVICE RESET command while the status register BSY bit is set to 1.
Hardware reset is a board requirement, not an MPC5200B function unless GPIO is used.
11.8.2
Software Reset
The host sets the device control register bit SRST to 1. Any subsequent setting and clearing of the SRST bit must be at least 5µs apart.
Figure 11-10
shows the Reset timing diagram.
11-36
NOTE
Ultra DMA Modes
HDMARDY
Host DMA ready during Ultra DMA data in bursts
HSTROBE
Host data strobe during Ultra DMA data out bursts
DDMARDY
Drive DMA ready during Ultra DMA data out bursts
DSTROBE
Drive data strobe during Ultra DMA data in bursts
STOP
Host stop ultra DMA bursts
NOTE
Table 11-40
gives timing characteristics.
MPC5200B Users Guide, Rev. 1
Description
Freescale Semiconductor
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