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ATA Register Interface
11.3.1.11
ATA Ultra DMA Timing 5 Register—MBAR + 0x3A28
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:7
udma_tzah
8:31
—
11.3.1.12
ATA Share Count Register—MBAR + 0x3A2C
msb0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:15
ata_share_cnt
16:31
—
11.3.2
ATA FIFO Registers—MBAR + 0x3A00
ATA uses a single FIFO that changes direction based on the Rx/Tx mode. Software controls direction change and flushes FIFO before
changing directions. FIFO memory is 512Bytes (Four 8 x 128 memories).
11-8
Table 11-11. ATA Ultra DMA Timing 5 Register
2
3
4
5
6
udma_tzah
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Minimum delay time required for output drivers to assert or negate from release state.
Count value is based on system clock operating frequency.
Reserved
Table 11-12.
2
3
3
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
This 16-bit value controls the length of the "time slot" assigned to ATA transactions when
PCI arbiter provides a grant to the ATA device. This is in IPB clocks. The arbiter will
maintain the grant to ATA for (at least) the ata_share_cnt value. When this value has
expired, ATA may be interrupted (paused) by the arbiter, to service other pending requests
for the AD bus.
Default value at reset is 128
Note: The maximal allowed setting is 0xFFFE.
Reserved
MPC5200B Users Guide, Rev. 1
7
8
9
10
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
ata_shre_cnt
7
8
9
10
ata_share_cnt
0
1
0
0
23
24
25
26
Reserved
0
0
0
0
Description
11
12
13
14
15
Reserved
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
Freescale Semiconductor
0
0
0
0
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