Chip Select Deadcycle Control Register—Mbar + 0X032C - Freescale Semiconductor MPC5200B User Manual

Bits Name
28 CW0
29 SLB0
30 —
31 BRE0
Note:
1. CDWF is defined as "critical doubleword word first".
2. The bits for Chip Select 0 (CS0) control CS Boot too.
3. With a clock ratio 1:1:1 (66:66:66 MHz) it is not possible to burst in Large Flash mode.
9.7.1.6 Chip Select Deadcycle Control Register—MBAR + 0x032C
msb 0 1
R Reserved
W
RESET: 0 0
16 17
R Reserved
W
RESET: 0 0
Bits Name
0:1 —
2:3 DC7
4:5 —
6:7 DC6
8:9 —
10:11 DC5
Freescale Semiconductor
Chip Select 0 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This
bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 0 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst
is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap
not capable. Long Burst capable means that peripheral can do 32-byte burst which hardware
will generate for cache line aligned XLB bursts (and CDWF if peripheral tagged as cache
wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Chip Select 0 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must
be set to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
Table 9-12. Chip Select Deadcycle Control Register
2 3 4 5 6
DC7 Reserved DC6
1 1 0 0 1
18 19 20 21 22
DC3 Reserved DC2
1 1 0 0 1
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
7 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
6 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
5 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10 11
Reserved DC5
1 0 0 1
23 24 25 26 27
Reserved DC1
1 0 0 1
Description
Programmer's Model
12 13 14 15
Reserved DC4
1 0 0 1 1
28 29 30 31 lsb
Reserved DC0
1 0 0 1 1
9-21