Chip Select 1 Configuration Register—Mbar + 0X0304 - Freescale Semiconductor MPC5200B User Manual

Bits Name
30 WO
31 RO
Note:
1. The reset values defined as "cfg" depends on the Reset Configuration.
2. Large Flash mode is used, if AS is set to 11 and DS is set to 00 or 01.
3. MOST/Graphics mode is used, if AS is set to 10 and DS is set to 11.
9.7.1.2 Chip Select 1 Configuration Register—MBAR + 0x0304
Chip Select 2 Configuration Register—MBAR + 0x0308
Chip Select 3 Configuration Register—MBAR + 0x030C
Chip Select 4 Configuration Register—MBAR + 0x0310
Chip Select 5 Configuration Register—MBAR + 0x0314
Chip Select 6 Configuration Register—MBAR + 0x0320
Chip Select 7 Configuration Register—MBAR + 0x0324
msb 0 1
R
W
RESET: 0 0
16 17
R MX Rsvd
W
RESET: 0 0
Bits Name
0:7 WaitP
8:15 WaitX
Freescale Semiconductor
Write Only bit—If bit is high, the peripheral is treated as a write-only device. An attempted
read access results in a bus error (as dictated by Chip Select Contro Register EBEE bit)
and/or an interrupt (as dictated by Chip Select Control Register IE bit). In any case, no
transaction is presented to the peripheral.
A bus error means the internal cycle is terminated with a transfer error acknowledge
(ips_xfr_err assertion to IP bus, TEA assertion to XL bus).
Read Only bit—If bit is high, the peripheral is treated as a read-only device. An attempted
write access results in a bus error (as specified by Chip Select Control Register EBEE bit)
and/or an interrupt (as specified by Chip Select Control Register IE bit). In any case, no
transaction is presented to the peripheral.
NOTE: This bit is high from Reset, indicating Boot Device is Read-Only.
Table 9-8. Chip Select 1 Configuration Register
Chip Select 2 Configuration Register
Chip Select 3 Configuration Register
Chip Select 4 Configuration Register
Chip Select 5 Configuration Register
Chip Select 6 Configuration Register
Chip Select 7 Configuration Register
2 3 4 5 6
WaitP
0 0 0 0 0
18 19 20 21 22
AA CE AS
0 0 0 0 0
Number of Wait States to insert. Can be applied as a prescale to Wait X or used by itself, as
dictated by the WTyp bits (see below). Wait States control how many PCI clocks the
corresponding CS pin remains active.
The base number of wait states to insert, or combined with WaitP as dictated by the WTyp
bits below.
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10
0 0 0 0
23 24 25 26
DS Bank WTyp
0 0 0 0
Description
Programmer's Model
11 12 13 14 15
WaitX
0 0 0 0
27 28 29 30 31 lsb
WS RS WO RO
0 0 0 0
0
0
9-15