Psc In Ac97 Mode - Freescale Semiconductor MPC5200B User Manual

Register
Port_Config
CR
Table 15-86 shows an example how to configure the PSC2 as SPI slave.
• use PSC2 as SPI slave
• 8bit data
• clock is active low, CPOL = 0;
• the first SCK edge is issued at the beginning of the data transfer; CPHA = 1
• msb first
• set the TFALARM level to 0x010, alarm occurs if 16 byte are in the TxFIFO
• set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO
• enable TxRDY interrupt
Register
CR
SICR 0x01009000
RFALARM
TFALARM
IMR
Port_Config 0x00000060
CR
15.3.3

PSC in AC97 Mode

After reset all PSCs are in UART mode. AC97 mode is chosen by setting the SICR[SIM] =0x3. The other
the same time. Only PSC1 and PSC2 support the AC97 mode. The AC97 controller supports two different AC97 modes, see
Transmitting and Receiving in "Normal" AC97 Mode
important register to configure the PSC for AC97 mode are:
• SICR register - select the Codec mode
• RFALARM, TFALARM
• CR register - enable or disable receiver and transmitter
• OP0, OP1 register - generate the reset pulse for the external device
• Port_config - select the right Pin-Muxing, see
Freescale Semiconductor
Value
0x00000600 Select the Pin-Muxing for PSC3 Codec mode, see:
Descriptions
0x05 Enable Tx and Rx
Table 15-86. 8-bit SPI Slave mode for PSC2
Value
0x0A Disable the Tx and Rx part for configuration if the PSC was enabled by the work
before.
Select the 8bit Codec SPI slave mode, msb first, CPOL = 0; CPHA = 1
0x000C set the RFALARM level to 0x00C
0x0010 set the TFALARM level to 0x010
0x0100 enable TxRDY interrupt
Select the Pin-Muxing for PSC2 Codec mode, see
0x05 Enable Tx and Rx
and Section 15.3.3.5, Transmitting and Receiving in "Enhanced" AC97 Mode.
- select the FIFO "Alarm" level
Chapter 2, Signal Descriptions
MPC5200B Users Guide, Rev. 1
PSC Operation Modes
Setting
Setting
Chapter 2, Signal Descriptions
SICR field should be initialized at
Chapter 2, Signal
Section 15.3.3.4,
The
15-61