Arbiter Master Priority Register (R/W)—Mbar + 0X1F68 - Freescale Semiconductor MPC5200B User Manual

Master Priority
M2
M1
M0
16.2.11 Arbiter Master Priority Register (R/W)—MBAR + 0x1F68
The Arbiter Master N Priority Register is used to set the software-programmable priority of each master. This register is used in conjunction
with the Arbiter Master Priority Enable Register to enable software-programmable master priorites, consequently ignoring internal,
hardware-wired signals. This register may be written at any time, and changes to this register become effective one clock after the register is
written.
Valid priority values range from 0 to 7, with 0 being the highest priority. Each of the eight fields in the register has the upper (fourth) bit
reserved. This allows for a possible future expansion to 16 priority levels. Currently, the reserved bits will always read as 0, and should be
written as 0 for future software compatibility.
msb 0 1
R Rsvd M7 Priority
W
RESET: 0 0
16 17
R Rsvd M3 Priority
W
RESET: 0 0
Bit Name
0 —
1:3 M7P
4 —
5:7 M6P
8 —
9:11 M5P
12 —
13:15 M4P
16 —
17:19 M3P
20 —
21:23 M2P
24 —
25:27 M1P
28 —
29:31 M0P
Freescale Semiconductor
Table 16-11. Hardware Assignments of Master Priority
1 BestComm
2 USB
7 e300 Core
Table 16-12. Arbiter Master Priority Register
2 3 4 5 6
Rsvd M6 Priority
0 1 0 0 0
18 19 20 21 22
Rsvd M2 Priority
0 1 0 0 0
Reserved
Master 7 Priority
Reserved
Master 6 Priority
Reserved
Master 5 Priority
Reserved
Master 4 Priority
Reserved
Master 3 Priority
Reserved
Master 2 Priority
Reserved
Master 1 Priority
Reserved
Master 0 Priority
MPC5200B Users Guide, Rev. 1
XLB Arbiter Registers—MBAR + 0x1F00
Description
7 8 9 10 11
Rsvd M5 Priority
1 0 0 0
23 24 25 26 27
Rsvd M1 Priority
1 0 0 0
Description
12 13 14 15
Rsvd M4 Priority
1 0 0 0 1
28 29 30 31 lsb
Rsvd M0 Priority
1 0 0 0 0
16-11