Pci Controller Type 0 Configuration Space - Freescale Semiconductor MPC5200B User Manual

Registers
Table 10-3. PCI Communication System Interface Register Map (continued)
Register
Offset
0x58
...
0x7C
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA4
...
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
...
0xFC
10.3.1

PCI Controller Type 0 Configuration Space

MPC5200B supplies a type 0 PCI Configuration Space header. These registers are accessible as an offset from MBAR
Map) or through externally mastered PCI Configuration Cycles.
Register Memory
The internal PCI controller can discover itself (by means of connecting an AD line [preferably AD24
to AD31]to the PCI _IDSEL input). It is essential, when the PCI interface is used as a Target, to enable
the internal PCI controller to access via the external PCI bus its own PCI registers. This is the only
available way in order to clear any error flag RWC bit (Read/WriteClear bit).
PCI
Reg DWord
Addr Offset
0x100 0x00
0x104 0x01 PCISCR
10-6
Mnemonic
PCIRPSR
PCIRSAR
PCIRTCR
PCIRER
PCIRNAR
PCIRLWR
PCIRDCR
PCIRSR
PCIRPDCR
PCIRFDR
PCIRFSR
PCIRFCR
PCIRFAR
PCIRFRPR
PCIRFWPR
Reg [31:24]
PCIIDR Device ID
MPC5200B Users Guide, Rev. 1
Name
Reserved
Rx Packet Size
Rx Start Address
Rx Transaction Control Register
Rx Enables
Rx Next Address
Rx Last Word
Rx Bytes Done Counts
Rx Status
Rx Packets Done Counts
Reserved
Rx FIFO Data
Rx FIFO Status
Rx FIFO Control
Rx FIFO Alarm
Rx FIFO Read Pointer
Rx FIFO Write Pointer
Reserved
NOTE
[23:16]
Status
(Section 3.2, Internal
[15:8] [7:0]
Vendor ID
Command
Freescale Semiconductor