Block Diagram—Fec; Features - Freescale Semiconductor MPC5200B User Manual

Overview
CLK/CNTL
tbus
requests
Controller
RISC
Controller
(RISC +
microcode)
MII
MDO
MDI
MDEN
I/O
Pad
MDIO
14.1.1

Features

The FEC incorporates several features/design goals that are key to its use:
• Support for different Ethernet physical interfaces:
— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface (industry standard)
• IEEE 802.3 full-duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• Support for full-duplex operation (200 Mbps throughput) with a minimum system clock rate of 50 MHz.
• Support for half-duplex operation (100 Mbps throughput) with a minimum system clock rate of 25 MHz.
• Large (1 Kbyte) on-chip transmit and receive FIFOs to support a variety of bus latencies.
• Retransmission from transmit FIFO following a collision (no processor bus utilization).
14-2
CommBus
SIF
tbus_addr
tbus_addr
Bus
tbusd_addr
MIB
Counters
MDC
Figure 14-1. Block Diagram—FEC
MPC5200B Users Guide, Rev. 1
Interrupt
CSR
FIFO Controller
Tx FIFO (1KByte)
Rx FIFO (1KByte)
T-bus
Transmit
TX_EN TX_CLK
TXD[3:0]
CRS,COL
TX_ER
MII/7-wire Data
Option
IP bus
FEC
Receive
RX_CLK
RX_DV
RXD[3:0]
RX_ER
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