Tlm And Tap Signal Descriptions; Test Reset (Trst); Test Clock (Tck); Test Mode Select (Tms) - Freescale Semiconductor MPC5200B User Manual

TLM and TAP Signal Descriptions

TDI
Update-DR or Run-Test/Idle
ENA
&
1
0
TMS
TCK
TRST-
21.3 TLM and TAP Signal Descriptions
21.3.1

Test Reset (TRST)

JTAG reset, active low. When asserted, any on-going JTAG operation is immediately aborted. All TAP state machines, including the TLM,
immediately enter the Test-Logic-Reset state. Other JTAG input signals (TCK, TMS, and TDI) have no effect while TRST is asserted. TDO
is immediately tri-stated.
21.3.2

Test Clock (TCK)

This is the JTAG clock. The (non-reset) behavior of the active TAP and TLM state machines is governed by the TMS value at the TCK rising
edge. TDI value is sampled at the TCK rising edge for all shift operations. All TDO non-reset transitions (including impedance) occur at the
TCK falling edge. All shift register capture operations occur at the TCK rising edge. All shift register Update operations occur at the TCK
falling edge.
21.3.3

Test Mode Select (TMS)

TAP state machine control, including TLM. The state of TMS at rising edges of TCK uniquely determines the state sequence of the TLM and
the active TAP state machines. See
21.3.4

Test Data In (TDI)

Serial test data input can be routed to any IR or DR, as determined by the state of the active TAP state machine and the contents of the active
IR. TDI is sampled at the TCK rising edge while the active TAP state machine is in either the Shift-IR or Shift-DR state.
21-4
ShiftDR
TAP State
ClockDR
Machine
UpdateDR
ShiftIR
ClockIR
UpdateIR
Figure 21-3. Generic Slave TAP
Figure 21-4. Inactive TAPs ignore TMS completely.
MPC5200B Users Guide, Rev. 1
DeviceID
BdyScan
Bypass
ShiftDR
ClockDR
UpdateDR
IR
SEL
TDO
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