Freescale Semiconductor MPC5200B User Manual page 649

Memory Map / Register Definition
TSEG13
0
...................................................................................................................................
1
1
TSEG22
0
0
....................................................................................................................................
1
1
19.5.7 MSCAN Receiver Flag Register (CANRFLG)—MBAR+0x0908 / 0x988
R
W
RESET:
Note: This register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is
writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
A flag can only be cleared when the condition which caused the setting is no longer valid and can only be cleared by software (writing a "1"
to the corresponding bit position). Every flag has an associated interrupt enable bit in the MSCAN Receive Interrupt Enable Register.
Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT(1:0) & TSTAT(1:0) flags which are read only; write of "1" clears flag; write
of "0" ignored.
19-10
Table 19-8. Time Segment 1 Values (continued)
TSEG12 TSEG11
0 1
1 1
1 1
Table 19-9. Time Segment 2 Values
TSEG21
0
0
1
1
Table 19-10. MSCAN Receiver Flag Register
msb 0 1 2
RSTAT[1:0]
0 0 0
MPC5200B Users Guide, Rev. 1
TSEG10
1
0
1
TSEG20
0
1
0
1
3 4 5 6
TSTAT[1:0]
0 0 0 0
Time segment 1
4 Tq clock cycles
15 Tq clock cycles
16 Tq clock cycles
Time segment 2
1 Tq clock cycle (a)
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
7 lsb
0
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