Freescale Semiconductor MPC5200B User Manual page 15

Table Of Contents
Paragraph
Number
15.3.3.4
15.3.4 PSC in SIR Mode ............................................................................................................................................15-58
15.3.4.1
15.3.4.2
15.3.4.3
15.3.5 PSC in MIR Mode ..........................................................................................................................................15-60
15.3.5.1
15.3.5.2
15.3.5.3
15.3.5.4
15.3.6 PSC in FIR Mode ............................................................................................................................................15-63
15.3.6.1
15.3.6.2
15.3.6.3
15.3.7 PSC FIFO System ...........................................................................................................................................15-64
15.3.7.1
15.3.7.2
15.3.8 Looping Modes ...............................................................................................................................................15-67
15.3.8.1
15.3.8.2
15.3.8.3
15.3.9 Multidrop Mode ..............................................................................................................................................15-68
16.1 Overview .................................................................................................................................................................16-1
16.1.1 Purpose ..............................................................................................................................................................16-1
16.1.1.1
16.1.1.2
16.1.1.2.1
16.1.1.2.2
16.1.1.3
16.1.1.4
16.1.1.4.1
16.1.1.4.2
16.2 XLB Arbiter Registers-MBAR + 0x1F00 ............................................................................................................16-3
16.2.1 Arbiter Configuration Register (R/W)-MBAR + 0x1F40 ..............................................................................16-3
16.2.2 Arbiter Version Register (R)-MBAR + 0x1F44 ............................................................................................16-5
16.2.3 Arbiter Status Register (R/W)-MBAR + 0x1F48 ..........................................................................................16-5
16.2.4 Arbiter Interrupt Enable Register (R/W)-MBAR + 0x1F4C .........................................................................16-6
16.2.5 Arbiter Address Capture Register (R)-MBAR + 0x1F50 ..............................................................................16-7
16.2.6 Arbiter Bus Signal Capture Register (R)-MBAR + 0x1F54 ..........................................................................16-7
16.2.7 Arbiter Address Tenure Time-Out Register (R/W)-MBAR + 0x1F58 ..........................................................16-8
16.2.8 Arbiter Data Tenure Time-Out Register (R/W)-MBAR + 0x1F5C ...............................................................16-9
16.2.9 Arbiter Bus Activity Time-Out Register (R/W)-MBAR + 0x1F60 ...............................................................16-9
16.2.10 Arbiter Master Priority Enable Register (R/W)-MBAR + 0x1F64 ..............................................................16-10
16.2.11 Arbiter Master Priority Register (R/W)-MBAR + 0x1F68 ..........................................................................16-11
16.2.12 Arbiter Snoop Window Register (RW)-MBAR + 0x1F70 ..........................................................................16-11
16.2.13 Arbiter Reserved Registers-MBAR + 0x1F00-1F3C, 0x1F74-1FFF ...........................................................16-13
TOC-14
Configuration Sequence for AC97 Mode .................................................................................................15-58
Block Diagram and Signal Definition for SIR Mode ...............................................................................15-58
Transmitting and Receiving in SIR Mode ................................................................................................15-59
Configuration Sequence Example for SIR Mode .....................................................................................15-59
Block Diagram and Signal Definition for MIR Mode ..............................................................................15-60
Transmitting and Receiving in MIR Mode ...............................................................................................15-61
Serial Interaction Pulse (SIP) ...................................................................................................................15-62
Configuration Sequence Example for MIR Mode ....................................................................................15-62
Block Diagram and Signal Definition for FIR Mode ...............................................................................15-63
Transmitting and Receiving in FIR Mode ................................................................................................15-63
Configuration Sequence Example for FIR Mode .....................................................................................15-64
RX FIFO ...................................................................................................................................................15-66
TX FIFO ...................................................................................................................................................15-67
Automatic Echo Mode ..............................................................................................................................15-67
Local Loop-Back Mode ............................................................................................................................15-67
Remote Loop-Back Mode ........................................................................................................................15-68
Chapter 16 XLB Arbiter
Prioritization ...............................................................................................................................................16-1
Bus Grant Mechanism ................................................................................................................................16-2
Bus Grant .............................................................................................................................................16-2
Parking Modes .....................................................................................................................................16-2
Configuration, Status, and Interrupt Generation ........................................................................................16-2
Watchdog Functions ...................................................................................................................................16-2
Timer Functions ...................................................................................................................................16-2
Other Tenure Ending Conditions .........................................................................................................16-3
MPC5200B Users Guide, Rev. 1
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Number
Freescale Semiconductor