Freescale Semiconductor MPC5200B User Manual page 132

Table 4-2. Reset Configuration Word Source Pins (continued)
Pkg Reset
Ball Config Pin
L03 RST_CFG13
N02 RST_CFG14
K02 RST_CFG15
Note:
1. If multipe settings are choosen the following priorities are valid:
1. large_flash_sel
2. boot_rom_mg
3. boot_rom_type
2. The boot_rom_size configuration signal doesn't influence the address and data bus width of the MOST Graphics boot
mode configuration. The maximum address bus width is fixed to 24 bit and the data bus width is fixed to 32 bit.
3. The boot_rom_size configurationsignal doesn't influence the address bus width of the Large Flash boot mode
configuration. The maximum address bus width is fixed to 26 bit.
4. The PCI controller is disabled, if booting in Large Flash or MOST Graphics mode is selected.
Freescale Semiconductor
CDM Reset
I/O Signal
Config
Name
Register Bit
ETH5 PORCFG[18]
ETH6 PORCFG[17]
ETH1 PORCFG[16]
MPC5200B Users Guide, Rev. 1
Config Signal
from CDM
boot_rom_size For non-muxed boot ROMs:
bit=0:8bit boot ROM data bus, 24bit
max boot ROM address bus
bit=1:16bit boot ROM data bus, 16bit
boot ROM address bus
For muxed boot ROMs:
boot ROM address is max 25 significant
bits during address tenure.
bit=0:16bit ROM data bus
bit=1:32bit ROM data bus
boot_rom_type bit=0:non-muxed boot ROM bus,
single tenure transfer.
bit=1:muxed boot ROM bus, with
address and data tenures,
ALE and TS active.
large_flash_sel bit=0:No Boot in Large Flash Mode
bit=1:Boot in Large Flash Mode
Reset Configuration
Description
2,3
1
1
1
1,3,4
4-5