Freescale Semiconductor MPC5200B User Manual page 285

Programmer's Model
Bits Name
13 SLB4
14 —
15 BRE4
16 CW3
17 SLB3
18 —
19 BRE3
20 CW2
21 SLB2
22 —
23 BRE2
24 CW1
25 SLB1
26 —
27 BRE1
9-20
Chip Select 4 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst
is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap
not capable. Long Burst capable means that peripheral can do 32-byte burst which hardware
will generate for cache line aligned XLB bursts (and CDWF if peripheral tagged as cache
wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Chip Select 4 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must
be set to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 3 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This
bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 3 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst
is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap
not capable. Long Burst capable means that peripheral can do 32-byte burst which hardware
will generate for cache line aligned XLB bursts (and CDWF if peripheral tagged as cache
wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Chip Select 3 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must
be set to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 2 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This
bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 2 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst
is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap
not capable. Long Burst capable means that peripheral can do 32-byte burst which hardware
will generate for cache line aligned XLB bursts (and CDWF if peripheral tagged as cache
wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Chip Select 2 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must
be set to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 1 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This
bit setting only applies in Large Flash or MOST Graphics Mode.
Chip Select 1 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst
is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap
not capable. Long Burst capable means that peripheral can do 32-byte burst which hardware
will generate for cache line aligned XLB bursts (and CDWF if peripheral tagged as cache
wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Chip Select 1 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must
be set to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
MPC5200B Users Guide, Rev. 1
Description
Freescale Semiconductor