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Host Control (HC) Operational Registers
16
17
R
W
RESET:
0
0
Bits
Name
16:31
FN
0:15
—
12.4.4.4
USB HC Periodic Start Register—MBAR + 0x1040
This register has a 14-bit programmable value that determines when is the earliest time HC should start processing the periodic list.
msb 0
1
R
W
RESET:
0
0
16
17
R
Reserved
W
RESET:
0
0
Bits
Name
0:17
—
18:31
PS
12.4.4.5
USB HC LS Threshold Register—MBAR + 0x1044
This register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum 8-Byte LS packet before
EOF. Neither the HC nor HCD are allowed to change this value.
msb 0
1
R
W
RESET:
0
0
12-18
18
19
20
21
22
0
0
0
0
0
FrameNumber—is incremented when HcFmRemaining is re-loaded. FN rolls over to 0 after
ffff.
When entering the USBOPERATIONAL state, this is automatically incremented. Content is
written to HCCA after HC has incremented the FN at each frame boundary and sent a SOF,
but before HC reads the first ED in that frame. After writing to HCCA, HC sets the
HcInterruptStatus StartofFrame.
Reserved
Table 12-17. USB HC Periodic Start Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
PeriodicStart—field is cleared after a hardware reset. PS is then set by HCD during HC
initialization. PS value is calculated roughly as 10% off from HcFmInterval. A typical value is
3E67.
When HcFmRemaining reaches the value specified, processing of periodic lists has priority
over Control/Bulk processing. HC then starts processing the Interrupt list after completing the
current Control or Bulk transaction in progress.
Table 12-18. USB HC LS Threshold Register
2
3
4
5
6
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
23
24
25
26
27
FN
0
0
0
0
Description
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
PS
0
0
0
0
Description
7
8
9
10
11
Reserved
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
Freescale Semiconductor
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