Memory Controller Registers (Mbar+0X0100:0X010C); Control Register—Mbar + 0X - Freescale Semiconductor MPC5200B User Manual

Memory Controller Registers (MBAR+0x0100:0x010C)

8.7.2 Control Register—MBAR + 0x0104
The 32-bit read/write Control register controls specific operations and generates some SDRAM commands. This register is reset only by a
power-up reset signal.
msb 0 1
R mode cke
_en
W
RESET: 0 0
16 17
R Reserved
W
RESET: 0 0
Bit Name
0 mode_en
1 cke
2 ddr
3 ref_en
4:6 —
7 hi_addr
8 —
9 drive_rule
8-22
Table 8-6. Memory Controller Control Register
2 3 4 5
ddr ref Rsvd
_en
0 0 0 0
18 19 20 21 22
mem_ Rsvd dqs_oe
ps
0 0 0 0
0 Mode register locked, cannot be written.
1 Mode register enabled, can be written.
0 MEM_CLK_EN negated (low).
1 MEM_CLK_EN asserted (high).
cke must be set to 1 to perform normal read and write operations. Set cke to 0 to put the
memory in Self Refresh or Power Down mode.
0 SDR mode.
1 DDR mode.
0 Automatic refresh disabled.
1 Automatic refresh enabled.
In general, refresh must be enabled, unless the system is known to access memory in a
pattern that is guaranteed to open every row in every bank within every refresh period
t . Some memory data sheets do not spec t
REF
= t x #rows.
REFI
NOTE: The number of Refresh commands required in t
the number of Read/Write commands required in t
Reserved
Control the use of internal address bits XLA[4:7] as row or column bits on the MEM_MA
bus. See Table 8-7.
Reserved (must be written 0)
0 "Tri-state except to write" mode: MPC5200B drives the MDQ and MDQS lines only
when necessary to perform write commands.
1 "Drive except to read" mode: MPC5200B tri-states the MDQ and MDQS lines only
when necessary to perform read commands.
"Drive except to read" mode prevents unterminated memory signals from floating for
extended periods. However, terminated routing is always recommended over
unterminated.
MPC5200B Users Guide, Rev. 1
6 7 8 9 10
hi_ Rsvd drive
addr _rule
0 0 0 0 0
23 24 25 26
Reserved
0 0 0 0 0
Description
, but spec t
REF
REF
11 12 13 14
ref_interval[0:5]
0 0 0 0
27 28 29 30
soft soft
_ref _pre
0 0 0 0
instead. In this case, t
REFI
is #rows; if refresh is disabled,
REF
is #rows x 4banks.
Freescale Semiconductor
15
0
31 lsb
Rsvd
0
REF