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20.8.3.1
Protocol Architecture
The Protocol Handler contains the State Machine, Rx Shadow Register, Tx Shadow Register, Rx Shift Register, Tx Shift Register, and
Loopback Multiplexer as shown in
DLOOP from DLCBCR2
loopback control
•
Rx & Tx Shift Registers
The Rx Shift Register gathers received serial data bits from the J1850 bus and makes them available in parallel form to the Rx
Shadow Register. The Tx Shift Register takes data, in parallel form, from the Tx Shadow Register and presents it serially to the State
Machine so that it can be transmitted onto the J1850 bus.
•
Rx & Tx Shadow Registers
Immediately after the Rx Shift Register has completed shifting in a byte of data, this data is transferred to the Rx Shadow Register
and RDRF or RXIFR is set and interrupt is generated if the interrupt enable bit (IE) in BDLC Control Register 1 is set. After the
transfer takes place, this new data byte in the Rx Shadow Register is available to the CPU, and the Rx Shift Register is ready to shift
in the next byte of data. Data in Rx Shadow Register must be retrieved by the CPU before it is overwritten by new data from the Rx
Shift Register.
Once the Tx Shift Register has completed its shifting operation for the current byte, the data byte in the Tx Shadow Register is
loaded into the Tx Shift Register. After this transfer takes place, the Tx Shadow Register is ready to accept new data from the CPU.
Freescale Semiconductor
Figure
20-12. Each block will now be described in more detail.
To Pad Drivers
RXB
Loopback
Multiplexer
State Machine
Rx Shift Register
Rx Shadow Register
8
To IP bus Interface & Rx/Tx Buffer's
Figure 20-12. BDLC Protocol Handler Outline
MPC5200B Users Guide, Rev. 1
TXB
Tx Shift Register
Tx Shadow Register
8
Functional Description
BDLC
20-29
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