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Chapter 17
Serial Peripheral Interface (SPI)
17.1
Overview
The following sections are contained in this document:
•
Section 17.2, SPI Signal Description
•
Section 17.3, SPI Registers—MBAR + 0x0F00
•
Section 17.4, Functional Description
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices.
Software can poll the SPI status flags or the SPI operation can be interrupt driven.
Figure 17-1
shows the SPI block diagram.
Baud Rate Generator
DIVIDER
2
4
8 16
32
SELECT
SPI Baud Rate Register
17.1.1
Features
The SPI has the following features:
•
Master mode and slave mode
•
Bi-directional mode
•
Slave-select output
•
Mode fault error flag with CPU interrupt capability
•
Double-buffered data register
•
Serial clock with programmable polarity and phase
•
Control of SPI operation during wait mode
Freescale Semiconductor
8-BIT Shift Register
64 128 256
Read Data Buffer
SPI Data Register
Shift Control Logic
MSTR
SPE
SP Control
SPI Status Register
Figure 17-1. Block Diagram—SPI
MPC5200B Users Guide, Rev. 1
LSBFE
Clock
Clock
Logic
SWOM
SPI Control Register 1
IP bus
Overview
S
M
MISO
M
S
MOSI
SCK
SS
S
M
SPI Control Register 2
17-1
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