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16
17
R
W
RESET
0
0
Bits
Name
0:31
Packets_Done
10.3.3.1.9
Tx Status PCITSR(RWC) —MBAR + 0x381C
msb 0
1
R
W
RESET
0
0
16
17
R
W
RESET
0
0
Bits
Name
0:6
Reserved
7
Normal
Termination
(NT)
8
Bus Error
type 3
(BE3)
9
Bus Error
type 2
(BE2)
Freescale Semiconductor
18
19
20
21
22
0
0
0
0
0
This status register indicates the number of packets transmitted and is active only if
continuous mode is in effect. The counter is reset if the following occurs:
•
Reset Controller bit, PCITER[RC], is asserted (normal way to restart continuous
mode)
•
Master Enable bit, PCITER[ME], becomes negated
Master enable can reset Packets_Done status without disturbing continuous mode
addressing. At any point in time, the total number of Bytes transmitted can be calculated
as:
(Packets_Done x Packet_Size) + Bytes_Done
assuming Packet_Size is the same for all restart sequences
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Unused. Software should write zero to these bits.
This flag is set when any packet terminates normally. It is NOT set for abnormally terminated
packets.
Note: Flag does not require clearing, but does not clear until 1 is written, in which case 0 is
read back (i.e., negated). The following flag bits operate similarly.
This flag is set whenever a Slave bus transaction attempts to write to a Read-Only register.
This flag bit is set regardless of the Bus error Enable bit (BE). If software is polling this Byte
and wishes to disregard this error it must mask this bit out.
No register bit corruption occurs for this (or any other) bus error case.
This flag is set whenever a Slave bus transaction attempts to write to a Reserved register (an
entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus
error Enable bit (BE). If software is polling this Byte and wishes to disregard this error it must
mask this bit out.
MPC5200B Users Guide, Rev. 1
23
24
25
26
Packets_Done
0
0
0
0
Description
7
8
9
10
NT
BE3
BE2
BE1
rwc
rwc
rwc
rwc
rwc
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
Registers
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
FE
SE
RE
TA
IA
rwc
rwc
rwc
rwc
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
0
0
0
10-29
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