Freescale Semiconductor MPC5200B User Manual page 558

After the stop bits are sent, if no new character is in the Tx holding register, the TxD output remains high (mark condition) and the Tx empty
bit, SR[TxEMP], is set. Transmission resumes and TxEMP is cleared when the CPU loads a new character into the PSC Tx buffer (TB).
• If the transmitter receives a disable command, it continues until any character in the Tx shift register is completely sent.
• If the transmitter is reset through a software command, operation stops immediately.
• If the clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted.
• If CTS is negated in the middle of a transmission, the character in the shift register is sent and TxD remains in mark state until CTS
is reasserted.
• If the transmitter is forced to send a continuous low condition by issuing a send break command, the transmitter ignores the state of
CTS.
• If the transmitter is programmed to automatically negate RTS when a message transmission completes, RTS must be asserted
manually before a message is sent.
In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed, RTS is negated one
bit-time after the character in the shift register is completely transmitted. The transmitter must be manually re-enabled by reasserting RT
before the next message is to be sent.
Figure 15-4 shows the transmitter functional timing information.
TxD
Transmit
Enabled
SR [TxRDY]
internal
module
select
3
CTS
4
RTS
NOTE:
1. Cn = transmit characters
2. W = write
3. MR2[TxCTS] = 1
4. MR2[TxRTS] = 1
15.3.1.4 Receiving in UART Mode
After a hardware reset, all PSCs are in UART mode. The receiver is enabled through its CR, as described in
(0x08)—CR. Figure 15-5 shows the receiver functional timing.
Freescale Semiconductor
C1 in transmission
1
C1 C2
2
W W
1
C1 C2
Manually asserted
by - command
BIT SET
Figure 15-4. Timing Diagram—Transmitter
MPC5200B Users Guide, Rev. 1
C3 Break
W W W
C3 Start C4 Stop
break break
PSC Operation Modes
C4
W W W
C5 C6
not
transmitted
Manually
asserted
Section 15.2.5, Command Register
S
C6
15-47