Freescale Semiconductor MPC5200B User Manual page 562

Signal
TxD Transmitter Serial Data Output—Data is shifted out on TxD on the falling or rising edge of the clock source.
Transfers can be specified as either lsb or msb first. TxD is held low when Tx is disabled or idle.
- data shifted out on the rising edge of CLK if SICR[ClkPol] = 0
- data shifted out on the falling edge of CLK if SICR[ClkPol] = 1
and
- data send msb first if SICR[SHDIR] = 0
- data send lsb first if SICR[SHDIR] = 1
RxD Receiver Serial Data Input—Data received on RxD is sampled on the falling or rising edge of the clock
signal. Transfers can be specified as either lsb or msb first.
- data sampled on the rising edge of CLK if SICR[ClkPol] = 1
- data sampled on the falling edge of CLK if SICR[ClkPol] = 0
and
- data sampled msb first if SICR[SHDIR] = 0
- data sampled lsb first if SICR[SHDIR] = 1
Frame Frame Sync—In Codec mode Frame can be driven from an external Codec or can be generate by the
internal clock logic. Frame can be programmed as active High or active Low.
- the frame sync input from the external Codec if SICR[GenClk] = 0
- the frame sync output to the external Codec if SICR[GenClk] = 1
and
- frame sync is active low if SICR[SyncPol] = 0
- frame sync is active high if SICR[SyncPol] = 1
CLK Bit Clock— In Codec mode CLK is:
• - the clock input from the external Codec if SICR[GenClk] = 0
• - the clock output to the external Codec if SICR[GenClk] = 1
Mclk Clock output for an external Codec
15.3.2.2 Codec Clock and FrameSync Generation
The serial BitClk and the FrameSync can either be inputs that come from an external Codec device, or they can be internally generated by the
PSC and provided as outputs to the external device, under control of bit SICR[GenClk]. When the bit SICR[GenClk] is set to zero then the
BitClk and the FrameSync are inputs. In this case the FrameSync width can be anything from one BitClk period up to the total FrameSync
length/period minus one BitClk. If the GenClk bit set to one, then the MPC5200 PSC generate the BitClk and the FrameSync signal.
Figure 15-8 shows how the PSC generate the clocks.
CDM
f
system
Mclk divider
MclkDiv[8:0] + 1
Freescale Semiconductor
Table 15-78. PSC Signal Description for Codec Mode
PSC
BitClk divider
CCR[8:23]
Figure 15-8. Clock Generation Diagram for Codec Mode
MPC5200B Users Guide, Rev. 1
Description
Frame divider
CCR[0:7]
CTUR[0:7]
PSC Operation Modes
Mclk
BitClk
Frame
15-51