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Bits
Name
30
DRT
31
LOOP
14.5.11
FEC Hash Register—MBAR + 0x3088
The read-only R_HASH register provides address recognition information from the Rx block about the frame currently being received. These
bits provide information used in the address recognition subroutine.
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0
FCE_DC
1
MULTICAST
2:7
HASH
8:31
—
14.5.12
FEC Tx Control Register—MBAR + 0x30C4
This X_CNTRL register is read/write and is written to configure the transmit block. This register is cleared at system reset. Bits 29:30 should
be modified only when ETHER_EN = 0.
msb 0
1
R
W
RESET:
0
0
Freescale Semiconductor
Disable Receive on Transmit
0 = Rx path operates independently of Tx
(use for full-duplex or to monitor Tx activity in half-duplex mode).
1 = Disable frames reception while transmitting
(normally used for half-duplex mode).
Internal Loopback—If set, transmitted frames are looped back internal to the device and
transmit output signals are not asserted. The system clock is substituted for TX_CLK when
LOOP is asserted. DRT must be set to 0 when asserting LOOP.
Table 14-20. FEC Hash Register
2
3
4
5
6
HASH
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
This is a read-only view of the R_CNTRL register FCE bit.
Set if current Rx frame contained a multi-cast destination address, indicating DA LSB was
set. Cleared if current Rx frame does not correspond to a multi-cast address.
Corresponds to "hash" value of current Rx frame's destination address. Hash value is a
6-bit field extracted from least significant portion of CRC register.
Reserved
Table 14-21. FEC Tx Control Register
2
3
4
5
6
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
7
8
9
10
11
Reserved
0
0
0
0
FEC Registers—MBAR + 0x3000
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
14-21
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