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10.3.3.2.1
Rx Packet Size PCIRPSR(RW) —MBAR + 0x3880
msb 0
1
R
W
RESET
0
0
16
17
R
W
RESET
0
0
Bits
Name
0:31
Packet_Size
10.3.3.2.2
Rx Start Address PCIRSAR (RW) —MBAR + 0x3884
msb 0
1
R
W
RESET
0
0
16
17
R
W
RESET
0
0
Bits
Name
0:31
Start_Add
10.3.3.2.3
Rx Transaction Control Register PCIRTCR(RW) —MBAR + 0x3888
msb 0
1
R
Reserved
W
RESET
0
0
Freescale Semiconductor
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Packet_Size[15:2]
0
0
0
0
0
The user writes this register with the number of bytes for Receive Controller to fetch over
PCI. The two low bits are hardwired low; only 32-bit data transfers to the FIFO are allowed.
Writing to this register also completes a Restart Sequence as long as Master Enable bit,
PCIRER[ME], is high and Reset Controller bit, PCIRER[RC], is low.
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
The user writes this register with the desired Starting Address for the current packet. This
is the address which will be first presented on the external PCI bus and then
auto-incremented as necessary. This register will not increment as the PCI packet
proceeds.
2
3
4
5
6
PCI_cmnd
0
0
1100
MPC5200B Users Guide, Rev. 1
7
8
9
10
Packet_Size[31:16]
0
0
0
0
23
24
25
26
0
0
0
0
Description
7
8
9
10
Start_Add
0
0
0
0
23
24
25
26
Start_Add
0
0
0
0
Description
7
8
9
10
0
0
0
11
12
13
14
0
0
0
0
27
28
29
30
31 lsb
Packet_Siz[1:0]
0
0
0
0
11
12
13
14
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
Max_Retries
0
0
0
0
Registers
15
0
0
15
0
0
15
0
10-35
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