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13.15.17 SDMA Initiator Priority 4 Register—MBAR + 0x1240
SDMA Initiator Priority 5 Register—MBAR + 0x1241
SDMA Initiator Priority 6 Register—MBAR + 0x1242
SDMA Initiator Priority 7 Register—MBAR + 0x1243
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:7
IPR4
Initiator Priority register for initiator 4 (or Task4 if PtdControl[16]=1)
Same bit layout as IPR0
8:15
IPR5
Initiator Priority register for initiator 5 (or Task5 if PtdControl[16]=1)
Same bit layout as IPR0
16:23
IPR6
Initiator Priority register for initiator 6 (or Task6 if PtdControl[16]=1)
Same bit layout as IPR0
24:31
IPR7
Initiator Priority register for initiator 7 (or Task7 if PtdControl[16]=1)
Same bit layout as IPR0
13.15.18 SDMA Initiator Priority 8 Register—MBAR + 0x1244
SDMA Initiator Priority 9 Register—MBAR + 0x1245
SDMA Initiator Priority 10 Register—MBAR + 0x1246
SDMA Initiator Priority 11 Register—MBAR + 0x1247
msb 0
1
R
W
RESET:
0
0
Freescale Semiconductor
Table 13-17. SDMA Initiator Priority 4 Register
SDMA Initiator Priority 5 Register
SDMA Initiator Priority 6 Register
SDMA Initiator Priority 7 Register
2
3
4
5
6
IPR4
0
0
0
0
0
18
19
20
21
22
IPR6
0
0
0
0
0
Table 13-18. SDMA Initiator Priority 8 Register
SDMA Initiator Priority 9 Register
SDMA Initiator Priority 10 Register
SDMA Initiator Priority 11 Register
2
3
4
5
6
IPR8
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
BestComm DMA Registers—MBAR+0x1200
7
8
9
10
11
0
0
0
0
23
24
25
26
27
0
0
0
0
Description
7
8
9
10
11
0
0
0
0
12
13
14
15
IPR5
0
0
0
0
0
28
29
30
31 lsb
IPR7
0
0
0
0
0
12
13
14
15
IPR9
0
0
0
0
0
13-15
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