Fec Interrupt Enable Register—Mbar + 0X3008; Fec Rx Descriptor Active Register—Mbar + 0X3010 - Freescale Semiconductor MPC5200B User Manual

FEC Registers—MBAR + 0x3000
14.5.3 FEC Interrupt Enable Register—MBAR + 0x3008
The IMASK register provides control over the interrupt events allowed to generate an interrupt. All implemented bits in this CSR are R/W.
This register is cleared by a hardware reset. If corresponding bits in both the IEVENT and IMASK registers are set, the interrupt is signalled
to the CPU. The interrupt signal remains asserted until 1 is written to the IEVENT bit (write 1 to clear) or a 0 is written to the IMASK bit.
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0 HBEEN
1 BREN
2 BTEN
3 GRAEN
4 TFIEN
5 —
6 —
7 —
8 MIIEN
9 —
10 LCEN
11 CRLEN
12 XFUNEN
13 XFERREN
14 RFERREN
15:31 —
14.5.4 FEC Rx Descriptor Active Register—MBAR + 0x3010
The FEC descriptor active register is a command register which should be written by the user to indicate that the receive descriptor ring has
been updated (empty receive buffers have been produced by the driver with the E bit set).
Whenever the register is written the R_DES_ACTIVE bit is set. This is independent of the data actually written by the user. When set, the
FEC will poll the receive descriptor ring and process receive frames (provided ETHER_EN is also set). Once the FEC polls a receive
descriptor whose ownership bit is not set, then the FEC will clear the R_DES_ACTIVE bit and cease receive descriptor ring polling until the
user sets the bit again, signifying additional descriptors have been placed into the receive descriptor ring.
14-14
Table 14-11. FEC Interrupt Enable Register
2 3 4 5 6
Reserved
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Heartbeat Error Interrupt Enable
Babbling Receiver Interrupt Enable
Babbling Transmitter Interrupt Enable
Graceful Stop Interrupt Enable
Transmit Frame Interrupt Enable
Reserved
Reserved
Reserved
MII Interrupt Enable
Reserved
Late Collision Enable
Late Collision Enable
Transmit FIFO Underrun Enable
Transmit FIFO Error Enable
Receive FIFO Error Enable
Reserved
MPC5200B Users Guide, Rev. 1
7 8 9 10 11
Rsvd
0 0 0 0
23 24 25 26 27
Reserved
0 0 0 0
Description
12 13 14 15
Rsvd
0 0 0 0 0
28 29 30 31 lsb
0 0 0 0 0
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