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7.3.2.1.14
GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34
Table 7-34. GPS GPIO Simple Interrupt Interrupt Types Register
msb 0
1
R
ITYP7
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:15
ITYP[0:7]
16:31
—
7.3.2.1.15
GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38
Table 7-35. GPS GPIO Simple Interrupt Master Enable Register
msb 0
1
R
Reserved
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Freescale Semiconductor
2
3
4
5
6
ITYP6
ITYP5
ITYP4
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 7.
ITYP7—bits 0:1 controls GPIO_SINT_7 (ETH_16 pin)
ITYP6—bits 2:3 controls GPIO_SINT_6 (ETH_15 pin)
ITYP5—bits 4:5 controls GPIO_SINT_5 (ETH_14 pin)
ITYP4—bits 6:7 controls GPIO_SINT_4 (ETH_13 pin)
ITYP3—bits 8:9 controls GPIO_SINT_3 (USB1_9 pin)
ITYP2—bits 10:11 controls GPIO_SINT_2 (PSC3_8 pin)
ITYP1—bits 12:13 controls GPIO_SINT_1 (PSC3_5 pin)
ITYP0—bits 14:15 controls GPIO_SINT_0 (PSC3_4 pin)
00 = Interrupt on any transition
01 = Interrupt on rising edge
10 = Interrupt on falling edge
11 = Interrupt on pulse (any two transitions)
Reserved
2
3
4
5
6
ME
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
ITYP3
ITYP2
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
General Purpose I/O (GPIO)
12
13
14
15
ITYP1
ITYP0
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
7-45
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