Freescale Semiconductor MPC5200B User Manual page 565

PSC Operation Modes
• FrameSync is low true
• lsb first, transfer starts one cycle after the leading edge of FrameSync
• set Mclk frequency to 33MHz
• set Bitclk frequency to 250 KHz
• FrameSync every 35 BitClk
• set FrameSync width to 3 BitClk
TFALARM
• set the level to 0x010, alarm occurs if 16 byte are in the TxFIFO
• set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO
• enable TxRDY interrupt
Register
CR
SICR
cdm_psc2_bitclk_config
cdm_clock_enable_register
CCR
CTUR
RFALARM
TFALARM
IMR
Port_Config
CR
15.3.2.4 Transmitting and Receiving in ESAI Mode (Enhanced Serial Audio Interface)
The ESAI transmission is similar to the "Soft Modem" mode. Therefore the configuration is the same like described in
Transmitting and Receiving in "Soft Modem" Codec Mode.
one data word per frame. To enable the ESAI mode the SICR[ESAI] bit must be set. The PSC calculate how many data words the transmitter
will send and how many data the receiver will expect.
15-54
Table 15-80. 32-Bit "Soft Modem"Master Mode
Value
0x0A Disable the Tx and Rx part for configuration if the PSC was enabled
by the work before.
0x3FA00000 Select the 32bit Codec mode, lsb first, DTS1 = 1, master mode
divide the f
0x800F
Section 5.5.12, PSC2 Mclock Config Register—MBAR + 0x022C
0x00000040 enable Mclk, see
0x0214
0x22830000 select the BitClk and FrameSync frequency
0x02 select the FrameSync width
0x000C set the RFALARM level to 0x00C
0x0010 set the TFALARM level to 0x010
0x0100 enable TxRDY interrupt
0x00000070 Select the Pin-Muxing for PSC2 Codec mode, Mclk output enabled,
Chapter 2, Signal Descriptions
see
0x05 Enable Tx and Rx
The different is, that the ESAI protocol allow to transmit and receive more than
Figure 15-10 shows the ESAI transmission
MPC5200B Users Guide, Rev. 1
Setting
clock frequency from 528 to 33MHz Mclk, see
system
Section 5.5.6, CDM Clock Enable Register—MBAR +
diagram.
Section 15.3.2.3,
Freescale Semiconductor