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Fast Ethernet Controller (FEC)
Address: 0xFC03_00C4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–5
Reserved, must be cleared.
4
Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause frame is
RFC_PAUSE
received and the transmitter pauses for the duration defined in this pause frame. This bit automatically clears
when the pause duration is complete.
3
Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC stops
TFC_PAUSE
transmission of data frames after the current transmission is complete. At this time, GRA interrupt in the EIR
register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control PAUSE frame.
Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter pauses due
to user assertion of GTS or reception of a PAUSE frame, the MAC may continue transmitting a MAC Control
PAUSE frame.
2
Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should only
FDEN
be modified when ECR[ETHER_EN] is cleared.
1
Heartbeat control. If set, the heartbeat check performs following end of transmission and the HB bit in the status
HBC
register is set if the collision input does not assert within the heartbeat window. This bit should only be modified
when ECR[ETHER_EN] is cleared.
0
Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted is
GTS
complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway, the
GRA interrupt is asserted immediately. After transmission finishes, clear GTS to restart. The next frame in the
transmit FIFO is then transmitted. If an early collision occurs during transmission when GTS is set, transmission
stops after the collision. The frame is transmitted again after GTS is cleared. There may be old frames in the
transmit FIFO that transmit when GTS is reasserted. To avoid this, clear ECR[ETHER_EN] following the GRA
interrupt.
19.4.12 Physical Address Lower Register (PALR)
PALR contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition
process to compare with the DA (destination address) field of receive frames with an individual DA. In
addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting
PAUSE frames. This register is not reset and you must initialize it.
Address: 0xFC03_00E4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
19-18
Figure 19-11. Transmit Control Register (TCR)
Table 19-15. TCR Field Descriptions
Figure 19-12. Physical Address Lower Register (PALR)
MCF5329 Reference Manual, Rev 3
8
7
6
5
RFC_
PAUSE TFC_
Description
8
PADDR1
Access: User read/write
4
3
2
1
0
FDEN HBC GTS
PAUSE
0
0
0
0
0
Access: User read/write
7
6
5
4
3
2
1
0
Freescale Semiconductor
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