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Registers
Bits
Name
11
System error
Enable
(SE)
12
Retry abort
Enable
(RE)
13
Target Abort
Enable
(TAE)
14
Initiator Abort
error
Enable
(IAE)
15
Normal
termination
Enable (NE)
16:31
Reserved
10.3.3.2.5
Rx Next Address PCIRNAR(R) —MBAR + 0x3890
msb 0
1
R
W
RESET
0
0
16
17
R
W
RESET
0
0
Bits
Name
0:31
Next_Address
10.3.3.2.6
Rx Last Word PCIRLWR(R) —MBAR + 0x3894
msb 0
1
R
W
RESET
0
0
10-38
User writes this bit high to enable CPU Interrupt generation in the case of system error
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that Multi-Channel DMA is controlling operation, but in such a case software should be
polling the status bits to prevent a possible lock-up condition.
User writes this bit high to enable CPU Interrupt generation in the case of retry abort
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that Multi-Channel DMA is controlling operation, but in such a case, software should poll the
status bits to prevent a possible lock-up condition.
User writes this bit high to enable CPU Interrupt generation in the case of target abort
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that Multi-Channel DMA is controlling operation, but in such a case software should poll the
status bits to prevent a possible lock-up condition.
User writes this bit high to enable CPU Interrupt generation in the case of initiator abort error
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that Multi-Channel DMA is controlling operation, but in such a case software should poll the
status bits to prevent a possible lock-up condition.
User writes this bit high to enable CPU Interrupt generation at the conclusion of a normally
terminated packet transmission. This may or may not be desirable depending on the nature
of program control by Multi-Channel DMA or the processor core.
Unused. Software should write zero to these bits.
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
This status register contains the next (unread) PCI address and is updated at the
successful completion of each PCI data beat. It represents a Byte address and is updated
with a user-written Start_Add value when Start_Add is reloaded. This register is intended
to be accurate even if an abnormal PCI bus termination occurs.
2
3
4
5
6
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
Next_Address
0
0
0
0
23
24
25
26
27
Next_Address
0
0
0
0
Description
7
8
9
10
11
Last_Word
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
Freescale Semiconductor
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