Spi Control Register 2—Mbar + 0X0F01 - Freescale Semiconductor MPC5200B User Manual

SPI Registers—MBAR + 0x0F00
Bit Name
6 SSOE Slave Select (SS) Output Enable—bit is enabled only in master mode by asserting SSOE and
SPIDDR bit 3 as shown in
7 LSBFE SPI LSB-First Enable—bit does not affect the position of the msb and lsb in the data register.
Reads and writes of the data register always have the msb in bit 7.
SPIDDR Bit 4
(DDR3)
0
0
1
1
17.3.2 SPI Control Register 2—MBAR + 0x0F01
msb 0
R
W
RESET: 0
Bit Name
0:5 — Reserved
6 SPISWAI SPI Stop in Wait Mode—bit is used for power conservation while in wait mode.
7 SPC0 Serial Pin Control Bit 0—working with the MSTR control bit, this bit enables bidirectional pin
configurations as shown in
17-4
Table
0 = Data is transferred most significant bit first.
1 = Data is transferred least significant bit first.
Table 17-3. SS Input/Output Selection
SSOE
0 SS input with MODF feature
1 General-purpose input
0 General-purpose output
1 SS output
Table 17-4. SPI Control Register 2
1 2
Reserved
0 0
0 = SPI clock operates normally in wait mode
1 = Stop SPI clock generation when in wait mode
Table
MPC5200B Users Guide, Rev. 1
Description
17-3.
Master Mode
3 4 5
0 0 0
Description
17-5.
Slave Mode
SS input
SS input
SS input
SS input
6 7 lsb
SPISWAI SPC0
0 0
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