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ATA FIFO is controlled by 32-bit registers. These registers are located at an offset from MBAR of 0x3a00. Register addresses are relative to
this offset. Therefore, the actual register address is:
Hyperlinks to the ATA FIFO registers are provided below:
•
ATA Rx/Tx FIFO Data Word Register
•
ATA Rx/Tx FIFO Status Register
•
ATA Rx/Tx FIFO Control Register
11.3.2.1
ATA Rx/Tx FIFO Data Word Register—MBAR + 0x3A3C
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:31
FIFO_Data_Word
11.3.2.2
ATA Rx/Tx FIFO Status Register—MBAR + 0x3A40
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:8
—
9
Err
Freescale Semiconductor
MBAR + 0x3A00 + register address
(0x3A3C)
(0x3A40)
(0x3A44)
Table 11-13. ATA Rx/Tx FIFO Data Word Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
The FIFO data port. Reading from this location "pops" data from the FIFO, writing
"pushes" data into the FIFO. During normal operation the BestComm Controller
pushes data here.
Note: ONLY full long-word access is allowed. If all byte enables are not asserted
when accessing this location, a FIFO error flag is generated.
Table 11-14. ATA Rx/Tx FIFO Status Register
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
Error—flag bit is essentially the logical "OR" of other flag bits and can be polled for detection
of any FIFO error. After clearing the offending condition, writing 1 to this bit clears flag.
MPC5200B Users Guide, Rev. 1
•
ATA Rx/Tx FIFO Alarm Register
•
ATA Rx/Tx FIFO Read Pointer Register
•
ATA Rx/Tx FIFO Write Pointer Register
7
8
9
10
FIFO_Data_Word
0
0
0
0
23
24
25
26
FIFO_Data_Word
0
0
0
0
Description
7
8
9
10
Err
UF
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
ATA Register Interface
(0x3A48)
(0x3A4C)
(0x3A50)
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
OF
Full
HI
LO
Emty
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
0
0
0
0
11-9
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