Freescale Semiconductor MPC5200B User Manual page 569

PSC Operation Modes
LRCK (Frame)
SCLK (CLK)
SDATA
start of Frame
Table 15-84 shows an example how to configure the PSC1 as I2S master. For the slave mode the bit SICR[GenClk] must be cleared and the
configuration of the CCR register can be ignored.
• use PSC1 as I2S master
• 32bit data, MSB first
• SCLK frequency 1 MHz
• FrameSync width 40 bit
• data shifted out on the falling edge of SCLK
• data transfer starts one CLK cycle after the FrameSync is active
• Frame starts with LRCK low
• set the TFALARM level to 0x010, alarm occurs if 16 byte are in the TxFIFO
• set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO
• enable TxRDY interrupt
Register
CR
SICR
cdm_psc1_bitclk_config
cdm_clock_enable_register
CCR
RFALARM
TFALARM
IMR
Port_Config
CR
15-58
DTS1
Data width
Frame length
Figure 15-12. I2S-Data Transmission
Table 15-84. 32-bit I2S Master Mode for PSC1
Value
0x0A Disable the Tx and Rx part for configuration if the PSC was enabled
by the work before.
0x2FE00000 Select the 32bit Codec I2S master mode, msb first, DTS1 =1
divide the f
0x8020
Section 5.5.11, PSC1 Mclock Config Register—MBAR + 0x0228
0x00000020 enable Mclk, see
0x0214
0x270F0000 set the FrameSync width (40 bit) and SCKL frequency
0x000C set the RFALARM level to 0x00C
0x0010 set the TFALARM level to 0x010
0x0100 enable TxRDY interrupt
0x00000006 Select the Pin-Muxing for PSC1 Codec mode, see
Descriptions
0x05 Enable Tx and Rx
MPC5200B Users Guide, Rev. 1
empty data bits until the
new data starts (zero)
Setting
clock frequency from 528 to 16 MHz Mclk, see
system
Section 5.5.6, CDM Clock Enable Register—MBAR +
start of Frame
Chapter 2, Signal
Freescale Semiconductor