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11.3.3.12
ATA Drive Device Status Register—MBAR + 0x3A7C
msb 0
1
R
BSY
DRDY
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0
BSY
1
DRDY
2:3
Data
4
DRQ
5:6
—
7
ERR
8
—
9
HUT
10
FR
11
FE
Freescale Semiconductor
Table 11-30. ATA Drive Device Status Register
2
3
4
5
6
Data
DRQ
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Indicates drive is busy processing a command.
Indicates drive is ready to accept executable commands.
Command dependent—Register is written only when ATA drive status register bits BSY and
DRQ equal 0 and DMACK is not asserted. If this register is written when BSY and DRQ bits
are set to 1, the result is indeterminate.
Register content is not valid when drive is in sleep mode.
Indicates drive is ready to transfer a data word.
Reserved
Set to 1 indicates ATA drive error register bits are valid.
Reserved
Host UDMA burst Terminate—Software can terminate UDMA burst prematurely by setting
this bit. Bits 15 through 10 are unaffected and retain previous values.
FIFO Reset—Hardware resets FIFO when the direction is switched from Tx to Rx. No
hardware reset is done for Rx to Tx switch. Software must verify FIFO is empty before filling
it for Tx. When bit 10 is set, FIFO is being reset and bits 15, 14, 13, 12, 11, 9 and 8 are
invalid.
Enable FIFO flush in Rx mode—For all commands except DEVICE RESET, this register is
written only when the ATA drive status register bits BSY and DRQ equal 0 and DMACK is not
asserted. If this register is written when BSY or DRQ bits are set to 1, the result is
indeterminate except for the DEVICE RESET command.
Register content is not valid when drive is in sleep mode.
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
ERR Rsvd HUT
FR
FE
0
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
ATA Register Interface
12
13
14
15
IE
UDMA
Read
Write
0
0
0
27
28
29
30
31 lsb
0
0
0
0
0
0
11-19
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