Gpw Wakeup Gpio Enables Register—Mbar + 0X0C00; Wakeup Gpio Registers—Mbar+0X0C - Freescale Semiconductor MPC5200B User Manual

Freescale semiconductor board users guide
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7.3.2.2
WakeUp GPIO Registers—MBAR+0x0C00
The WakeUp GPIO Register Set provides GPIO control for the 8 WakeUp GPIO pins. These pins are scattered throughout the pin groups, but
are all controlled in this module. It should be noted that WakeUp GPIO can operate as Simple Interrupt GPIO. Because of this, there are
separate registers to enable these pins as Wakeup interupts and/or Simple Interrupts. The distiniction between these two types of interrupts is
made according to the powered state of MPC5200B.
In Deep Sleep mode, the WakeUp Interrupt enables are used.
In all other modes, the Simple Interrupt enables are used.
In either of the above types of interrupts, we are referring to the WakeUp GPIO and the registers in this module. These are not to be confused
with the Simple Interrupt GPIO pins, which are controlled in the previous module, GPIO Standard.
This WakeUp GPIO register set uses 10 32-bit registers. These registers are located at an offset from MBAR of 0x0C00. Register addresses
are relative to this offset. Therefore, the actual register address is:
Hyperlinks to the WakeUp GPIO registers are provided below:
GPW WakeUp GPIO Enables Register
GPW WakeUp GPIO Open Drain Emulation Register
(0x0C04)
GPW WakeUp GPIO Data Direction Register
GPW WakeUp GPIO Data Value Out Register
GPW WakeUp GPIO Interrupt Enable Register
7.3.2.2.1
GPW WakeUp GPIO Enables Register—MBAR + 0x0C00
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:7
WGPIOe
8:31
Freescale Semiconductor
(0x0C00)
(0x0C08)
(0x0C0C)
(0x0C10)
Table 7-37. GPW WakeUp GPIO Enables Register
2
3
4
5
6
WGPIOe
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Bits to enable the operation of individual WaleUp GPIO pins.
Bit 0 controls GPIO_WKUP_7 (GPIO_WKUP_7 pin)
Bit 1 controls GPIO_WKUP_6 (GPIO_WKUP_6 pin)
Bit 2 controls GPIO_WKUP_5 (PSC6_1 pin)
Bit 3 controls GPIO_WKUP_4 (PSC6_0 pin)
Bit 4 controls GPIO_WKUP_3 (ETH_17 pin)
Bit 5 controls GPIO_WKUP_2 (PSC3_9 pin)
Bit 6 controls GPIO_WKUP_1 (PSC2_4 pin)
Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin)
0 = Pin not enabled for any GPIO use (default).
1 = Pin enabled for use as GPIO.
Reserved
MPC5200B Users Guide, Rev. 1
MBAR + 0x0C00 + register address
GPW WakeUp GPIO Individual Interrupt Enable Register
(0x0C14)
GPW WakeUp GPIO Interrupt Types Register
GPW WakeUp GPIO Master Enables Register
GPW WakeUp GPIO Data Input Values Register
GPW WakeUp GPIO Status Register
7
8
9
10
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
General Purpose I/O (GPIO)
(0x0C18)
(0x0C1C)
(0x0C20)
(0x0C24)
11
12
13
14
15
Reserved
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
0
0
7-47

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