Freescale Semiconductor MPC5200B User Manual page 699

Functional Description
Table 20-13. BDLC Transmitter VPW Symbol Timing for Integer Frequencies (continued)
Number
5 Start of Frame (SOF)
6 End of Data (EOD)
7 End of Frame (EOF)
8 Inter-Frame Separator (IFS)
Note:
1. The transmitter timing for this symbol depends upon the minimum detection time of the symbol by the receiver.
Table 20-14. BDLC Transmitter VPW Symbol Timing for Binary Frequencies
Number
1 Passive Logic 0
2 Passive Logic 1
3 Active Logic 0
4 Active Logic 1
5 Start of Frame (SOF)
6 End of Data (EOD)
7 End of Frame (EOF)
8 Inter-Frame Separator (IFS)
Note:
1. The transmitter timing for this symbol depends upon the minimum detection time of the symbol by the receiver.
Table 20-15. BDLC Receiver VPW Symbol Timing for Integer Frequencies
Number
1
Passive Logic 0
2 Passive Logic 1
3 Active Logic 0
4 Active Logic 1
5 Start of Frame (SOF)
6 End of Data (EOD)
7 End of Frame (EOF)
8 Inter-Frame Separator (IFS)
9 Break Signal (BREAK)
Note:
1. The receiver symbol timing boundaries are subject to an uncertainty of 1 t
20-20
Characteristic
1
1
1
Characteristic
1
1
1
Characteristic
MPC5200B Users Guide, Rev. 1
Symbol Min Typ
T 198 200
tva3
T 162 164
tvp3
T 238 240
tv4
T 298 300
tv5
Symbol Min Typ
T 65
tvp1
T 132 134
tvp2
T 132 134
tva1
T 65
tva2
T 208 210
tva3
T 170 172
tvp3
T 250 252
tv4
T 313 315
tv5
Symbol Min
T 32
rvp1
T 96
rvp2
T 96
rva1
T 32
rva2
T 164
rva3
T 164
rvp3
T 240
rv4
T 281
rv5
T 240
rv6
due to sampling considerations.
bdlc
Max Unit
202 t
bdlc
166 t
bdlc
242 t
bdlc
302 t
bdlc
Max Unit
67 69 t
bdlc
136 t
bdlc
136 t
bdlc
67 69 t
bdlc
212 t
bdlc
174 t
bdlc
254 t
bdlc
317 t
bdlc
Typ Max Unit
64 95 t
bdlc
128 163 t
bdlc
128 163 t
bdlc
64 95 t
bdlc
200 239 t
bdlc
200 239 t
bdlc
280 299 t
bdlc
--- --- t
bdlc
--- --- t
bdlc
Freescale Semiconductor