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FEC Tx FIFO Status Register—MBAR + 0x31A8
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:21
—
22:31
Alarm[9:0]
14.8.5
FEC Rx FIFO Read Pointer Register—MBAR + 0x319C
FEC Tx FIFO Read Pointer Register—MBAR + 0x31BC
The RFIFO_RDPTR and TFIFO_RDPTR are a FIFO-maintained pointer which point to the next FIFO location to be read. The read pointer
can be both read and written.
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:21
—
22:31
READ[9:0]
14-32
Table 14-35. FEC Rx FIFO Alarm Pointer Register
FEC Tx FIFO Alarm Pointer Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Reserved
0
0
0
0
0
Reserved
Alarm Pointer.
This pointer indicates the point at (or below) which to assert the FIFO alarm signal. This
value is compared with data or free bytes, depending upon the state of FIFO Transmit (FIFO
Transmit = "1", alarm measures data bytes).
Table 14-36. FEC Rx FIFO Read Pointer Register
FEC Tx FIFO Read Pointer Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Reserved
0
0
0
0
0
Reserved
Read Pointer.
This pointer indicates the next location to be read by the FIFO controller.
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
Alarm[9:0]
0
0
0
0
Description
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
READ[9:0]
0
0
0
0
Description
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
Freescale Semiconductor
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