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Chapter 1
Introduction
1.1
Overview
The digital communication networking and consumer markets require significant processor performance to enable operating systems and
applications such as VxWorks™, QNX™, JAVA and soft modems. High integration is essential to reducing device and systems costs. The
MPC5200B is specifically designed to meet these market needs while building on the family of microprocessors that use PowerPC™
architecture. For more information on PowerPC architecture, see "The Programming Environments Manual for 32-bit Implementations of the
PowerPC Architecture".
The MPC5200B integrates a high performance e300 core with a rich set of peripheral functions focused on communications and systems
integration. The e300 core design is based on the PowerPC™ core architecture. The MPC5200B incorporates an innovative I/O subsystem,
which isolates routine maintenance of peripheral functions from the embedded e300 core.
The MPC5200B supports a dual external bus architecture. It has a high speed SDRAM Bus interface that connects directly to the e300 core.
In addition, the MPC5200B has a LocalPlus Bus used as a generalized interface to system level peripheral devices and debug environments.
1.1.1
Features
Key features are shown below.
•
e300 core
— Superscalar architecture
— 760MIPS at 400MHz (-40 to +85
— 16k Instruction cache, 16k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard & Critical interrupt capability
•
SDRAM / DDR Memory Interface
— up to 132MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per Chip Select (Two CS lines available)
— 32-bit data bus
— Built-in initialization and refresh
•
Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices
— 8 programmable Chip Selects
— Non multiplexed data access using 8/16/32 bit databus with up to 26 bit address
— Short or Long Burst capable
— Multiplexed data access using 8/16/32 bit databus with up to 25 bit address
•
Peripheral Component Interconnect (PCI) Controller
— Version 2.2 PCI compatibility
— PCI initiator and target operation
— 32-bit PCI Address/Data bus
— 33 and 66 MHz operation
— PCI arbitration function
•
ATA Controller
— Version 4 ATA compatible external interface—IDE Disk Drive connectivity
•
BestComm DMA subsystem
— Intelligent virtual DMA Controller
— Dedicated DMA channels to control peripheral reception and transmission
— Local memory (SRAM 16kBytes)
•
6 Programmable Serial Controllers (PSC), configurable for:
— UART or RS232 interface
— CODEC interface for Soft Modem, Master/Slave CODEC Mode, I
— Full duplex SPI mode
Freescale Semiconductor
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MPC5200B Users Guide, Rev. 1
2
S and AC97
Overview
1-1
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