Bdlc Block Diagram - Freescale Semiconductor MPC5200B User Manual

Block Diagram
• Low Power Options
The BDLC module can save power in Disabled, Wait, and Stop modes. A complete description of what the BDLC module does
while in a low power mode can be found in
20.4 Block Diagram
bus clock
CPU Interface
bus clock
Protocol Handler
bus clock
MUX Interface
Figure 20-2 shows the organization of the BDLC module. The Buffers provide storage for data received and data to be transmitted onto the
J1850 bus. The Protocol Handler is responsible for the encoding and decoding of data bits and special message symbols during transmission
20-4
Section 20.3, Modes of Operation.
To CPU
CPU INTERFACE
BCR1 BSVR
BCR2
8
Control/ Status
TX Data
TX Shadow Register
8
TX Data
TX Shift Register
Protocol State Machine
Control/ Status
TX Data
Symbol Encoder/Decoder
TX Data
To Physical Interface
TXB
Figure 20-2. BDLC Block Diagram
MPC5200B Users Guide, Rev. 1
BDR BARD
8
RX Data
RX Shadow Register
8
RX Data
RX Shift Register
RX Data
RX Data
RX Digital
Filter
RX Data
Loopback
Multiplexer
RX Data
RXB
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