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Functional Description
PCI Bus
C/BE[3:0]
Command
0111
Memory-write
1000
Reserved
1001
Reserved
1010
Configuration
read
1011
Configuration
write
1100
Memory read
multiple
1101
Dual address
cycle
1110
Memory read
line
1111
Memory write
and invalidate
Though MPC5200B supports many PCI commands as an initiator, the Communication Sub-System Initiator interface is intended to use PCI
Memory Read, and Memory Write commands.
10.4.1.5
Addressing
PCI defines three physical address spaces: PCI memory space, PCI I/O space, and PCI configuration space. Address decoding on the PCI bus
is performed by every device for every PCI transaction. Each agent is responsible for decoding its own address. PCI supports two types of
address decoding: positive decoding and subtractive decoding. The address space which is accessed depends primarily on the type of PCI
command that is used.
10.4.1.5.1
Memory space addressing
For memory accesses, PCI defines two types of burst ordering controlled by the two low-order bits of the address: linear
incrementing(AD[1:0] = 0b00) and cache wrap mode (AD[1:0] = 0b10). The other two AD[1:0] encodings (0b01 and 0b11) are reserved.
10-48
Table 10-5. PCI Bus Commands (continued)
MPC5200B
MPC5200B
supports as
supports
Initiator
as Target
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes (DMA
Yes
access only)
MPC5200B Users Guide, Rev. 1
Definition
The memory write command accesses agents
mapped into PCI memory space.
--
--
The configuration read command accesses the 256
byte configuration space of a PCI agent.
The configuration read command accesses the 256
byte configuration space of a PCI agent.
For MPC5200B, the memory read multiple
command functions the same as the memory read
command. Cache line wrap is implemented when
XL Bus is the transaction initiator and it also wraps.
The dual address cycle command is used to
transfer a 64-bit address (in two 32-bit address
cycles) to 64-bit addressable devices. MPC5200B
device does not respond to this command.
The memory read line command indicates that an
initiator is requesting the transfer of an entire cache
line.For MPC5200B, the memory read line
functions the same as the memory read command.
Cache line wrap is not implemented.
The memory write and invalidate command
indicates that an initiator is transferring an entire
cache line, and, if this data is in any cacheable
memory, that cache line needs to be invalidated.
The memory write and invalidate functions the
same as the memory write command. Cache line
wrap is implemented.
Software must make sure that the cache line
register and max_beats register are set to the same
value and the packet size must be a multiple of the
cache line size.
This instruction is supported only by the TX SCPCI
initiator interface and when the MPC5200B acts as
a target.
Freescale Semiconductor
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