Ipbi Control Register And Wait State Enable -Mbar+0X0054 - Freescale Semiconductor MPC5200B User Manual

MPC5200B Memory Map
3.3.3.4 IPBI Control Register and Wait State Enable —MBAR+0x0054
The IPBI Control Register consists of the Enables for the Base Addresses set in Memory Map Space
msb 0 1
R Reserved
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:3 Reserved
4 CS7 Ena
5 CS6 Ena
6 Boot Ena
7:9 Reserved
10 CS5 Ena
11 CS4 Ena
12 CS3 Ena
13 CS2 Ena
14 CS1 Ena
15 CS0 Ena
16:30 Reserved
31 WSE
3-8
2 3 4 5
CS7 CS6 Boot
Ena Ena Ena
0 0 0 0
18 19 20 21 22
0 0 0 0 0
These bits are reserved.
Chip Select 7 Enable
Chip Select 6 Enable
Boot Enable
These bits are reserved.
Chip Select 5 Enable
Chip Select 4 Enable
Chip Select 3 Enable
Chip Select 2 Enable
Chip Select 1 Enable
Chip Select 0 Enable
These bits are reserved.
Wait State Enable bit. This bit should always be enabled when running an IP bus frequency
of >66MHz.
MPC5200B Users Guide, Rev. 1
6 7 8 9 10
Reserved CS5
Ena
1 0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
11 12 13 14 15
CS4 CS3 CS2 CS1 CS0
Ena Ena Ena Ena Ena
0 0 0 0
27 28 29 30 31 lsb
WSE
0 0 0 0 1
Freescale Semiconductor
0