Rx Fifo Control Register Pcirfcr(Rw) —Mbar + 0X38C8 - Freescale Semiconductor MPC5200B User Manual

Registers
R
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:8 Reserved
9 Receive Wait
Condition
(RXW)
10 UnderFlow
(UF)
11 OverFlow
(OF)
12 Frame Ready
(FR)
13 Full
14 Alarm
15 Empty
16:31 Reserved
10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) —MBAR + 0x38C8
msb 0 1
R Reserved
W
RESET 0 0
16 17
R
W
RESET 0 0
10-42
Reserved
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Unused byte. Software should write zero to these bits.
This flag bit indicates that the ipf_rcv bus is incurring wait states because there is not
enough room in the FIFO to accept the data without causing overflow. This bit will cause the
error outputs (fifoError, ipf_rcv_error, ipf_xmit_error) to assert unless the RXW_MASK bit in
the FIFO Control register is set. Resetting the FIFO will clear this condition and the flag bit
is cleared by writing a one to its bit position.
This flag bit indicates that the read pointer has surpassed the write pointer. In other words
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
This flag bit indicates that the write pointer has surpassed the read pointer. In other words
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
The FIFO has a complete Frame of data ready for transmission. This module
does not provide support for Data Framing applications, so this bit should be ignored.
The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the
state of the FIFO.
When the FIFO pointer is at or above the Alarm "watermark", as written by the user
according to the Alarm and Control registers settings, the Alarm bit is asserted, thus
automatically signalling to the DMA engine that the FIFO needs to be 'emptied'. By writing
a '1' to this location software can enforce re-evaluation of the alarm condition.
The FIFO is empty. This is not a sticky bit or error condition.
Unused. Software should write zero to these bits.
2 3 4 5 6
GR
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
RXW UF OF
rwc rwc rwc
0 0 0 0
23 24 25 26 27
Reserved
0 0 0 0
Description
7 8 9 10 11
1 0 0 1
23 24 25 26 27
Reserved
0 0 0 0
FR Full Alarm Empty
0 0 0 0 1
28 29 30 31 lsb
0 0 0 0 0
12 13 14 15
Reserved
0 0 0 0 0
28 29 30 31 lsb
0 0 0 0 0
Freescale Semiconductor