Receiving Ifr Exceptions; Special Bdlc Module Operations; Transmitting Or Receiving A Block Mode Message; Receiving An Ifr With The Bdlc Module - Freescale Semiconductor MPC5200B User Manual

Freescale semiconductor board users guide
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.
Once BDLC module Detects
EOF, IFR
reception is complete
20.8.7.2

Receiving IFR Exceptions

This basic IFR receiving flow can be interrupted for the same reasons as a normal message reception. The IFR receiving process can be
adversely affected due to a CRC error, an Invalid or Out of Range Symbol or due to a receiver overrun caused by the CPU failing to service
an RxIFR interrupt in a timely fashion. For a description of how these exceptions can affect the IFR receiving process, refer to
20.8.5.4, Receiving
Exceptions.
20.8.8

Special BDLC Module Operations

There are a few special operations which the BDLC module can perform. What follows is a brief description of each of these functions and
when they might be used.
20.8.8.1

Transmitting Or Receiving A Block Mode Message

The BDLC module, because it handles each message on a byte-by-byte basis, has the inherent capability of handling messages any number
of bytes in length. While during normal operation this requires the user to carefully monitor message lengths to ensure compliance with SAE
J1850 message limits, often in a production or diagnostic environment messages which exceed the SAE J1850 limits can be beneficial. This
is especially true when large amounts of configuration data need to be downloaded over the SAE J1850 network.
Freescale Semiconductor
Enter IFR Receive
Routine
Is DLCBSVR = $1C/$18?
(Error Detected)
No
Yes
Is DLCBSVR = $08?
(RxIFR)
No
B
Yes
Is DLCBSVR = $04?
(EOF)
No
A
Exit IFR Receive
Routine
Figure 20-18. Receiving An IFR With the BDLC module
MPC5200B Users Guide, Rev. 1
Yes
Discard received
IFR bytes
Read byte in DLCBDR
No
Is this an IFR
xmit reflection?
Yes
Store received IFR byte
(in case of LOA)
Store received IFR byte
B
Functional Description
B
Filter received IFR byte
Yes
Is this IFR
of any interest?
No
Set IMSG bit in DLCBCR1
A
Section
20-45

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