Table of Contents
Advertisement
XLB Arbiter Registers—MBAR + 0x1F00
16
17
R
W
RESET:
1
1
Bit
Name
0:31
BUSTO
16.2.10
Arbiter Master Priority Enable Register (R/W)—MBAR + 0x1F64
The Arbiter Master Priority Enable Register determines whether the arbiter uses the hard-wired or software programmable priority for a
master. The default is enabled for all masters. Both methods may be employed at the same time for different masters. This register may be
written to at any time, and the change becomes effective one clock after the register is written.
When enabled, the software programmable value in the Arbiter Master N Priority Register is used as the priority for the master. When
disabled, the priority assignment for each master is determined by the hardware-wired mNpri signals, as shown in
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:23
—
24
M7
25
M6
26
M5
27
M4
28
M3
29
M2
30
M1
40
M0
Master
Priority
M7–M4
M3
16-10
18
19
20
21
22
1
1
1
1
1
Bus Activity Time-out. Contains the value of the Bus Activity Time-out Counter. Values
represent increments of 1. Default value is 0xFFFFFFFF.
Table 16-10. Arbiter Master Priority Enable Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Rsvd
0
0
0
0
0
Reserved
Master 7 Priority Register Enable
Master 6 Priority Register Enable
Master 5 Priority Register Enable
Master 4 Priority Register Enable
Master 3 Priority Register Enable
Master 2 Priority Register Enable
Master 1 Priority Register Enable
Master 0 Priority Register Enable
Table 16-11. Hardware Assignments of Master Priority
—
Unused
0
PCI Target Interface
MPC5200B Users Guide, Rev. 1
23
24
25
26
BUSTO[16:31]
1
1
1
1
Description
7
8
9
10
Rsvd
0
0
0
0
23
24
25
26
M7
M6
M5
M4
0
1
1
1
Description
Description
27
28
29
30
31 lsb
1
1
1
1
Table
16-10.
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
M3
M2
M1
M0
1
1
1
1
Freescale Semiconductor
1
0
1
Advertisement
Table of Contents
