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Slice Timers
Bit
Name
Reserved
0:4
—
5
Run_ Wait A high indicates the Timer should run continuously while enabled. When the Timer counter
reaches terminal count it immediately resets to 0 and resumes counting. If the Run/Wait bit is
set low, the Timer Counter expires, but then waits until the Timer is cleared (either by writing 1
to the status bit or by disabling and re-enabling the Timer), before resuming operation.
6
Interrupt
CPU Interrupt is generated only if this bit is high. This bit does not affect operation of the Timer
Enable
Counter or Status Bit registers.
7
Timer
While this bit is high the Timer operates normally, while low the Timer is reset and remains idle.
Enable
8:32
—
Reserved
7.5.1.3
SLT 0 Count Value Register—MBAR + 0x0708
SLT 1 Count Value Register—MBAR + 0x0718
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:7
—
Reserved
8:31
Timer
Provides current state of the Timer counter. This register does not chodange while a read is in
Count
progress, but the actual Timer counter continues unaffected.
7-64
Table 7-53. SLT 0 Count Value Register
SLT 1 Count Value Register
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
TimerCount
0
0
0
0
23
24
25
26
27
TimerCount
0
0
0
0
Description
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
Freescale Semiconductor
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