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Memory Map and Registers
Table 20-7. BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment (continued)
BARD Offset Bits BO[4:0]
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Note:
1. The transmitter symbol timing adjustment is the same for binary and integer bus frequencies.
20.7.3.6
BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309
This register determines the divider prescaler value for the mux interface clock (f
f
are supported as input clock.
bdlc
msb 0
R
R7
W
RESET:
0
READ: any time
WRITE: write once in normal and emulation modes.
—
R7-R0
Rate Select (Bits 7-0)
These bits determine the amount by which the frequency of the system clock signal is divided to generate the MUX Interface clock (f
which defines the basic timing resolution of the MUX Interface. The value programmed into these bits is dependent on the chosen system
clock frequency. See
Table 20-9
divide by 256 are possible, but are not shown in the tables.
Although the maximum divider is 256, a divider which will generate a 1 MHz or 1.048576 MHz f
must be selected in order for J1850 communications to occur.
20-14
Corresponding Expected
Transceiver's delays (
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 20-8. BDLC Rate Select Register
1
2
R6
R5
0
0
and
Table 20-10
for example rate selects for different bus frequencies. All divisor values from divide by 1 to
MPC5200B Users Guide, Rev. 1
Transmitter Symbol Timing
µ
s)
Adjustment (
). Only integer multiple of the 1 MHz or 1.048576 MHz
bdlc
3
4
5
R4
R3
R2
0
0
0
NOTE
t
1
)
bdlc
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
6
7 lsb
R1
R0
0
0
)
bdlc
bdlc
Freescale Semiconductor
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