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13.15.14 SDMA Task Control C Register—MBAR + 0x1234
SDMA Task Control D Register—MBAR + 0x1236
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:15
TCRC
16:31
TCRD
13.15.15 SDMA Task Control E Register—MBAR + 0x1238
SDMA Task Control F Register—MBAR + 0x123C
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:15
TCRE
16:31
TCRF
Freescale Semiconductor
Table 13-14. SDMA Task Control C Register
SDMA Task Control D Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Task control register for task 12. Same bit layout as for TCR0
Task control register for task 13. Same bit layout as for TCR0
Table 13-15. SDMA Task Control E Register
SDMA Task Control F Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Task control register for task 14. Same bit layout as for TCR0
Task control register for task 15. Same bit layout as for TCR0
MPC5200B Users Guide, Rev. 1
BestComm DMA Registers—MBAR+0x1200
7
8
9
10
11
TCRC
0
0
0
0
23
24
25
26
27
TCRD
0
0
0
0
Description
7
8
9
10
11
TCRE
0
0
0
0
23
24
25
26
27
TCRF
0
0
0
0
Description
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
13-13
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