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Bits
Name
16:22
—
23
Int_min
24:30
—
31
Int_sec
7.6.3.9
RTC Test Register/Divides Register—MBAR + 0x0820
This register is used during manufacturing test to expedite RTC testing and is not intended to be a user register. However, no protection from
software access is provided.
msb 0
1
R
Rsvd
W
RESET:
1
1
16
17
R
W
RESET:
0
0
Bit
Name
0
—
1:7
PTERM
8:15
ETERM
16:31
—
Note: The 32.768KHz crystal frequency is divided by PTERM, which is then divided by ETERM to produce a 1 second
time interval. It is conceivable that a system might wish to adjust these values to produce a more locally accurate clock
rate. However, be aware that these values are affected by reset. Therefore, any adjustment value must be stored and
retrieved from non-volatile memory. Further, the adjustment could only increase the clock rate, not decrease it.
Freescale Semiconductor
Reserved
Periodic interrupt at each minute rollover. High indicates interrupt has occurred.
Cleared by writing 1 to this bit position.
Reserved
Periodic interrupt at each second rollover. High indicates interrupt has occurred.
Cleared by writing 1 to this bit position.
Table 7-64. RTC Test Register/Divides Register
2
3
4
5
6
PTERM
1
1
1
1
1
18
19
20
21
22
0
0
0
0
0
Reserved
Prescale Termination value, the number of 32KHz clocks per 7-bit prescale counter.
Default at reset is the maximum (and proper) value of 128 decimal. Any value lower than
this causes the RTC to run fast.
External Termination value, the number of prescaled counts per 8-bit external counter.
Default at reset is the maximum (and proper) value of 256 decimal. Any value lower than
this causes the RTC to run fast.
Reserved
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
1
1
1
1
23
24
25
26
27
Reserved
0
0
0
0
Description
Real-Time Clock
12
13
14
15
ETERM
1
1
1
1
1
28
29
30
31 lsb
0
0
0
0
0
7-73
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