Freescale Semiconductor MPC5200B User Manual page 426

msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0:10 —
11 PRSC
12 OCIC
13 PSSC
14 PESC
Freescale Semiconductor
Table 12-22. USB HC Rh Port1 Status Register
2 3 4 5 6
Reserved
0 0 0 0 0
18 19 20 21 22
Reserved LSDA
0 0 0 0 0
Reserved
PortResetStatusChange—bit is set at the end of the 10ms port reset signal.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 = Port reset not complete
1 = Port reset complete
PortOverCurrentIndicatorChange—bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 = No change in POCI
1 = POCI has changed
PortSuspendStatusChange—bit is set when the full resume sequence completes. Sequence
includes a 20s resume pulse, LS EOP, and 3ms resychronization delay.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 = Resume not complete
1 = Resume complete
PortEnableStatusChange—bit is set when hardware events cause the PES bit to be cleared.
Changes from HCD writes do not set this bit.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 = No change in PES
1 = Change in PES
MPC5200B Users Guide, Rev. 1
Host Control (HC) Operational Registers
7 8 9 10 11
PRSC
0 0 0 0 0
23 24 25 26 27
PPS Reserved PRS
1 0 0 0 0
Description
12 13 14 15
OCIC PSSC PESC CSC
0 0 0 0
28 29 30 31 lsb
POCI PSS PES CCS
0 0 0 0
12-23