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Programmer's Model
9.7.2.2
SCLPC Start Address Register—MBAR + 0x3C04
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:31
Start Address
9.7.2.3
SCLPC Control Register—MBAR + 0x3C08
msb 0
1
R
Reserved
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:4
—
5:7
CSX
8:13
—
14
Flush
15
RWb
9-24
Table 9-14. SCLPC Start Address Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Address of the first byte in the packet to be sent. This value must be aligned with the
"BPT" (Bytes Per Transaction) field, described below. This address will appear
directly at the peripheral and is completely independent of XLB address decoding
logic.
Table 9-15. SCLPC Control Register
2
3
4
5
6
CSX
0
0
0
0
0
18
19
20
21
22
Reserved
0
0
0
0
0
Reserved
This field should be written with the Chip Select number associated with each DMA
transaction.
Note: LPC configuration registers associated with this CS also affect SCLPC
transactions. The two work together.
Reserved
If set to 1, enables the assertion of SCLPC requestor at the completion of a *Read*
Packet, regardless of the actual state of the physical fifo ALarm. Requestor will
de-assert once the fifo goes empty. This is the fix for the familiar "Stale Read Data"
fifo problem.
Read - Write bar. Controls direction of DMA transaction.
1 = SCLPC will read from the peripheral, i.e. Fifo Receive
0 = SCLPC will write to the peripheral, i.e. Fifo Transmit
MPC5200B Users Guide, Rev. 1
7
8
9
10
Start Address
0
0
0
0
23
24
25
26
Start Address
0
0
0
0
Description
7
8
9
10
Reserved
0
0
0
0
23
24
25
26
DAI
Reserved
0
0
0
0
Description
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
Flush
RWb
0
0
0
0
27
28
29
30
31 lsb
BPT
0
0
0
0
Freescale Semiconductor
0
0
0
0
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