Freescale Semiconductor MPC5200B User Manual page 398

3. Write command code 0xEF to command register to execute SET FEATURES command. This sets the data transfer protocol to
multiword DMA with desired mode.
Data transfers into DMA differ from a PIO transfer in that:
• Data is transferred using the DMA channel.
• A single interrupt is issued at command completion.
The Host initializes the DMA channel prior to issuing DMA mode commands. The drive asserts an interrupt when data transfer is complete.
The DMA command protocol is as follows:
1. HOST: Read status or alternate status register until BSY and DRQ are both 0. (ATA-4, 41, 48).
2. HOST: Write device/head register with appropriate DEV bit value to select drive. (ATA-4, 45).
3. HOST: Wait 400 ns, read status or alternate status register until BSY & DRQ are set to 0. The required drive is then assured to be
selected.
4. HOST: Write required command parameters to the features, sector count, sector number, cylinder high, cylinder low, and
device/head registers. (ATA-4, chapter 7).
5. HOST: Write command code to command register for drive to start processing command using parameters from the command
block registers. (ATA-4, 41).
6. DRIVE: If no drive error exists, set BSY=1 and begin processing command.
7. HOST: Wait 400ns, read status or alternate status register to ensure valid contents.
8. DRIVE: Set BSY=1 or BSY=0 && DRQ=1.
9. DRIVE: Assert DMARQ when ready, transfer data per multiword DMA timing or ultra DMA protocol.
10. HOST: Assert DMACK, negate
protocol. Transfers are 16-bit wide from the data port. DMA data out (drive→host) transfers are processed by a series of reads to
the data port. Each read transfers the data that follows the previous read. DMA in data (host→drive) transfers are processed by a
series of writes to this port. Each write transfers the data that follows the previous write. Results are indeterminate if data port is
written during a DMA data out or data port is read during a DMA data in transfers.
11. DRIVE: Negate DMARQ when transfer is complete.
12. DRIVE: Set error status in error register if error exists.
13. DRIVE: Clear BSY and DRQ.
14. DRIVE: Assert INTRQ if Host has enabled nIEN (set to 0) in command control register. This register is written by the host to
enable interrupt from the drive by clearing nIEN bit to 0. INTRQ is in a high impedance state if nIEN bit is set to 1.
When host sets command control register bit SRST to 1, software can reset selected drive. However, the command control register must be
written while DMACK is not asserted. Bit 0 must be cleared to 0.
1. HOST: To clear pending interrupt, read status register (regardless of nIEN status).
2. DRIVE: If enabled by nIEN (nIEN = 0), negate INTRQ.
3. DMA command completes.
DMA Command
Command
READ DMA
WRITE DMA
Figure 11-8 shows the DMA command protocol flow diagram.
Freescale Semiconductor
CS CS
[0] and [1] when ready to transfer data per multiword DMA timing or ultra DMA
Table 11-38. DMA Command Parameters
Code Sector
Features
Count
C8h Yes
CAh Yes
MPC5200B Users Guide, Rev. 1
Parameters Used (Registers)
Sector
Number/LBA HI/LO/LBA
Yes Yes
Yes Yes
ATA Bus Background
Cylinder
Device/Head/LBA
Yes D/H Both
Yes D/H Both
11-33